1. Field of the Invention
The present invention relates to a circuit device for interfacing between several processing units equipped with microprocessors.
2. Background Information
As known, when interconnecting devices having processors with different architectures, a problem arises with regard to homogeneous interconnection of processors especially if they work according to different methods and operations. In other words, there is a difficulty in making both the interconnected processors work as a unique homogeneous system where, however, the constituting parts normally work according to procedures, frequencies, operation logies very different from each other.
Besides, when interfacing between several processors or between computerized systems, comprising processors, there is a need for compact circuitry, preferably integrated, which is able to handle a plurality of functions relative to interfacing between the processors themselves.
Such functions are those relating to: handling controls for synchronous, asynchronous and DMA communication modes, for example, between the processor of a host computer and the processor of a speech processing module; for the control and handling of interrupt signals relative to the processor present in a speech processing module (Motorola 68000 processor), as well as for the handling of reset signals; for the decoding of all signals travelling over the interfacing device; for timing; and all distributed circuitries which at present realize and comply with such functions.
In order to solve such problems, various interconnection systems are in use. For instance, interconnection by bus is the system that allows exploitation of storage present in single processors, semaphorizing them by means of software or firmware in such a way as to make each processor work singularly by stopping in stand-by the other, and vice versa.
When processors are then coupled via serial lines, it is possible to use DMAs (direct memory accesses) or interrupt systems which in the same way allow to individuate, in suitable times, signals from both processor sending them over the connection bus, i.e., over the serial line, without creating collision between transmitted signal packets.
However, such solutions give rise to onerous circuit difficulties as hardware structures or software or firmware solutions are necessary which make the whole system massive and therefore slows down data transmission between processors which have to be interfaced to each other, thus subtracting process capacity from the interested processors.
Moreover, the circuitry required goes against the need for a unique assembled and as compact as possible system. Thus reducing the complexities and likewise the possibilities of errors during operation too, which are characteristic of the more complex systems is descrable.